The present disclosure relates to built-in self-test (BIST) devices and methods, and more specifically, to structures and methods that stagger the start of BIST controllers and that stagger the start of groups of BIST engines controlled by the BIST controllers.
Silicon chips are being populated with increasing amounts of memory and logic as technologies progress. Power demand due to simultaneous use of these memories can cause disturbances to the power supply. These voltage disturbances can cause memories or logic to fail due to operation outside of the rated voltage range.
As more memories are integrated onto chips and the power density of those chips increases (increasing watts per square mm) the risk that simultaneous access of memories will cause logic or memory failures increases greatly. Typical chip function will operate a subset of memory content at any one point in time in order to manage power consumption. Power supply decoupling capacitance can be added to chip and board designs to mitigate transient voltage disturbances and larger power supplies and/or improved cooling mechanisms can be applied to support higher power usage in general, but all of these solutions are expensive in terms of chip area and system cost.
Memory BIST (built-in self test) is designed to operate as many memories simultaneously as possible while still avoiding false failures due to over test (due to exceeding the power specification for a certain chip design). For a given chip design this might be a small subset, whereas for other chip designs this could include virtually all memories. In addition, memory BIST should be able to test with some margin compared to the normal functional application in order to produce good SPQL (shipped product quality level) while minimizing impacts to yield.